1. Field of the Invention
This invention relates generally to semiconductor devices having molded housings. More particularly, the invention pertains to an apparatus and method for suppressing power supply voltage modulation and noise in packaged integrated circuits (ICs) such as leaded or unleaded chip carriers, dual-in-line packages (DIP), pin-grid array packages, leads-over-chip (LOC) packages, quad flat packages (QFP) and other packages.
2. State of the Art
A modern packaged integrated circuit (IC) comprises one or more encapsulated semiconductor die(s) or chip(s) within a protective xe2x80x9cpackagexe2x80x9d of plastic, ceramic, or other material. A plurality of external connections, typically designed for soldering, are connected to bond pads on the encapsulated die(s), enabling the die(s) to be electrically connected to an external electrical apparatus including a power supply.
Despite the relatively short distance between external terminals of a semiconductor device and the integrated circuit chip or die within the package, inductance is present from outer leads, inner leads, wire bonds and other conductors connected to the power supply. The high switching speeds of digital circuits require relatively high levels of instantaneous current to achieve the desired switching operations. In such high frequency switching operations of integrated circuits (IC), the inductance results in the coupling of transient energy into the power supply circuit to modulate the power supply voltage. The modulation of the power supply voltage will be equal to the product of the inductance and the time rate of change of the current through the conductor. The power supply modulation, generally referred to as power supply noise, may cause malfunctions in the IC circuit, degrading the overall performance of the resin-encapsulated integrated circuit and/or rendering the packaged IC unusable.
To reduce this problem, it has been proposed in Japanese Patent No. A6045504 of Miyazaki Oki Electric Co. Ltd. to provide a plurality of metal plates attached to the upper and lower surfaces of a leadframe by an insulative adhesive. A reduction in xe2x80x9clead cross-talk noisexe2x80x9d is claimed, although none of the plates is shown as being electrically connected to the circuit to provide capacitance.
It has been found, however, that a more effective device to reduce lead inductance is to provide leads of greater size and/or of shorter length.
Thus, in U.S. Pat. No. 5,032,895 of Horiuchi et al., a quad flat package (QFP) structure is shown in which a metal plate is adhered to the leadframe beneath the chip. The metal plate is connected to an external power supply and serves as a power lead for the chip. The size of the metal plate reduces the inductance of the device. Use of a decoupling capacitor is not disclosed.
U.S. Pat. No. 5,105,257 of Michii discloses the use of large coplanar trapezoidal power leads and a ground lead underlying the chip of a semiconductor device for reducing lead inductance and increasing heat transfer. No capacitor is shown.
A much more effective solution for decoupling transient coupled energy in the integrated circuit is to connect a decoupling capacitor across the affected portion(s) of the circuit. The capacitor counters the transient voltage changes and suppresses the resulting noise.
An early suppressor of the undesirable electrical coupling comprised a decoupling capacitor mounted on a circuit board, e.g., separate from the packaged IC, but connected across the power supply, i.e., across the power plane and ground plane leads. The length of the conductive path between the external decoupling capacitor and the chip circuit was, of necessity, lengthy. In many instances, the path length resulted in high inductance and caused high voltage drops due to such inductance.
Subsequently, decoupling capacitors have been mounted on the IC package itself in order to reduce the conductive lead length between the capacitor and the chip. For example, a monolithic multilayer decoupling ceramic chip capacitor may be attached to the underside of an IC package.
Recent developments have resulted in the need for an improved decoupling capacitor. First, the numbers of inner leads in a package have escalated, requiring that lead width be reduced and lead length increased. As a result of longer, narrower leads, lead inductance and electrical coupling between adjacent inner leads become operational problems under more benign conditions.
In addition, the power dissipation required of many newer chip packages has been significantly increased, such that coupling produces more severe voltage aberrations and noise in the power supply circuit.
Also, newer electronic equipment operates at higher clock rate frequencies which, of course, increases the incidence of coupling and the resulting noise.
Furthermore, certain particular applications for packaged integrated circuits may be much more demanding. For example, in some applications, ICs must be capable of withstanding high ionizing radiation without failure.
Various decoupling schemes have been developed to cope with these recent developments. In U.S. Pat. No. 4,680,613 of Daniels et al., for example, a metal ground plane is attached to the leadframe with encapsulant during the encapsulation process and becomes a ground lead with low inductive impedance. In addition, however, a multilayer capacitor (MLC) chip is placed within the polymer IC package remote from the chip.
Ideally, the decoupling capacitor should be as close to the chip or die as possible to reduce the lead induction and maximize its suppressive effect. Thus, the capacitor will be encapsulated within the IC package and typically will closely parallel the die surface. Various attempts to produce such a package are shown in the patent literature as follows:
U.S. Pat. No. 4,410,905 of Grabbe shows a decoupling structure for a semiconductor device, wherein a chip is mounted atop a beryllium oxide sliver. The upper surface of a chip carrier has an interdigitated lead pattern, and is bonded by a bonding agent to the underside of the beryllium oxide sliver.
In U.S. Pat. No. 4,891,687 of Mallik et al., a chip carrier and a leadframe have interposed therebetween a pair of parallel metal plates comprising an upper ground plane and a lower power plane. The metal plates are joined by Kapton(copyright) tape, and a chip is mounted within a space in the plates to the power plane. Decoupling capacitors may be installed between the two metal plates.
In U.S. Pat. No. 5,140,496 of Heinks et al., one or more decoupling capacitors are placed directly atop or beneath the chip and connected by multiple wire bonds to power supply connections on the chip surface.
U.S. Pat. No. 4,994,936 of Hernandez shows a packaged integrated circuit in which a decoupling capacitor is attached to the upper die surface or to the underside of the leadframe.
Japanese Patent Application No. 64-305219 of Seiko Epson Corporation describes a semiconductor device in which an electrode is bonded to a portion of an underlying leadframe by a dielectric material. The die is then bonded to the electrode with an insulative film. The leadframe portion and electrode are then connected to the die to form a capacitor.
Japanese Patent No. A 3276747 of NEC Corporation describes a 2-layer chip support member including leadframe planes having an interposed insulation layer. The two planes are electrically connected to a Vcc power source and a ground power source, respectively, to provide noise-preventing capacitance.
In Japanese Patent No. A 4162657 of Hitachi Ltd., a semiconductor device is shown which has a two-part leadframe with parallel tab parts joined by a dielectric material such as ceramic. A die is mounted on the upper tab part and the two tab parts are electrically connected across the power supply to provide a capacitor.
Japanese Patent No. A 4188759 of Mitsubishi Electric Corporation discloses a semiconductor device having a planar capacitor formed of two leadframes joined by an insulator, the capacitor underlying the chip.
Although the state of the art in package configuration is continually improving, ever-increasing demands for further miniaturization, circuit complexity, higher clock rates, higher production speed, reduced cost, improved product uniformity and reliability require further improvements in packaged semiconductor devices by which electrical coupling and inductance noise are minimized or eliminated.
The invention comprises an apparatus and method for suppressing power supply voltage modulation and noise in packaged integrated circuits (ICs) such as leaded or unleaded chip carriers, dual-in-line packages (DIP), pin-grid array packages, leads-over-chip (LOC) packages, quad flat packages (QFP) and other packages.
In the present invention, an integrated circuit device includes a plurality of integral flat capacitors closely aligned with and parallel to a major surface of the die (chip). One or more of the capacitors may be connected across power supply leads and/or other lead pairs to reduce coupling and suppress noise produced thereby. The present invention further includes a method for forming the integrated circuit device including the integrated circuit and decoupling capacitor(s).
The integrated circuit device includes a multiple layer leadframe. One layer of the leadframe comprises a first conductive layer of the decoupling capacitor(s). A second layer of the leadframe comprises a second, opposite conductive layer of the capacitor(s), and the two layers are joined by an interposed dielectric material to create the capacitor(s). Together, the layers may be looked upon as a xe2x80x9cpaddlexe2x80x9d or xe2x80x9cdie support platformxe2x80x9d to which a die is downbonded.
One or both of the leadframe layers are subdivided to form multiple capacitors having different capacitances and/or adapted to optimally operate at different switching frequencies. Each capacitor may be connected across a different portion of the integrated circuit, enabling custom design of capacitors appropriate for each circuit portion. In one embodiment, one leadframe layer may be a single xe2x80x9cplatexe2x80x9d common to a plurality (or all) of the capacitors and connected to the power supply ground plane Vss, or to another common voltage plane.
The decoupling capacitor(s) are closely positioned to the die, i.e. chip, enabling the use of short wire leads. Thus, conductor inductances between the capacitor(s) and the bond pads on the die are much reduced.
The invention may be applied to a leads-over-chip device by including a third (uppermost) leadframe member which includes lead fingers which partially overlie the active surface of the chip and outer leads connected to the lead fingers for connecting the device to a circuit board or other apparatus.
The device, including one or more integral decoupling capacitors, is encapsulated by a plastic material such as epoxy, using transfer molding techniques or other encapsulation methods known in the art.
The plurality of special capacitors produces more effective decoupling of coupled electrical aberrations in various circuit portions. In addition, the overall inductance in the integrated circuit conductors is reduced. Furthermore, it is evident that one or more of the capacitors may be configured for use as circuit elements other than a decoupler/noise suppressor. Thus, one or more of the capacitors may be connected to the IC circuitry to provide a capacitor connected thereto rather than having to build a capacitor in the integrated circuit on the chip.
The invention is illustrated in the following figures, wherein the elements are not necessarily shown to scale.